Field of the Disclosure
The present disclosure relates to a liquid crystal display, and more particularly, to a fringe field switching type liquid crystal display. Although the present disclosure is suitable for a wide scope of applications, it is particularly suitable for preventing damage on a transparent conductive layer when the transparent conductive layer is exposed for connecting with metal layers in etching processes.
Discussion of the Background
Nowadays, various flat panel displays (or ‘FPD’) are developed for overcoming many drawbacks of the cathode ray tube (or ‘CRT’) such as heavy weight and bulkiness. The flat panel display devices include a liquid crystal display device (or ‘LCD’), a field emission display (or ‘FED’), a plasma display panel (or ‘PDP’), an organic light emitting display device (or ‘OLED’) and an electrophoresis display device (or ‘ED’).
A display panel of the flat panel display includes a thin film transistor substrate having a thin film transistor allocated in each pixel region arrayed in a matrix manner. For example, the liquid crystal display device represents video data by controlling light transmission of a liquid crystal layer by an electric field. Depending on a direction of the electric field, the LCD can be classified in two major types; one is a vertical electric field type and the other is a horizontal electric field type.
For the vertical electric field type LCD, a common electrode on an upper substrate and a pixel electrode on a lower substrate are facing each other for forming an electric field having a direction perpendicular to the substrates. A twisted nematic (TN) liquid crystal layer disposed between the upper substrate and the lower substrate is driven by the vertical electric field. The vertical electric field type LCD has an advantage of a higher aperture ratio, while it has a disadvantage of a narrower viewing angle of about 90 degree.
For the horizontal electric field type LCD, a common electrode and a pixel electrode are formed on the same substrate in parallel. A liquid crystal layer disposed between an upper substrate and a lower substrate is driven in In-Plane-Switching (or ‘IPS’) mode by an electric field parallel to the substrates. The horizontal electric field type LCD has an advantage of a wider viewing angle over 160 degrees and a response speed faster than that of the vertical electric field type LCD. However, the horizontal electric field type LCD may have disadvantages such as a low aperture ratio and a low transmission ratio of the back light.
In the IPS mode LCD, for example, in order to form an in-plane electric field, the gap between the common electrode and the pixel electrode may be larger than the gap (or “Cell Gap”) between the upper substrate and the lower substrate, and in order to get enough strength of the electric field, the common electrode and the pixel electrode need to be formed of a strip pattern having a certain width. Between the pixel electrode and the common electrode of the IPS mode LCD, the electric field horizontal with respect to the substrate is formed. However, just over the pixel electrode and the common electrode, there is no electric field. That is, the liquid crystal molecules disposed just over the pixel electrodes and the common electrodes can not be driven but maintain the initial conditions (i.e., the initial alignment direction). As the liquid crystal molecules in the initial condition cannot control the light transmission properly, the aperture ratio and the luminescence can be degraded.
For resolving these disadvantages of the IPS mode LCD, the fringe field switching (or ‘FFS’) type LCD driven by the fringe electric field has been proposed. The FFS type LCD comprises the common electrode and the pixel electrode with the insulating layer there-between. The pixel electrode and the common electrode are overlapped in a vertical direction. Otherwise, the pixel electrode and the common electrode do not overlap each other but are separated from each other by a gap setting narrower than the gap between the upper substrate and the lower substrate. A fringe electric field having a parabola shape is formed in the space between the common electrode and the pixel electrode as well as over these electrodes. Therefore, most of liquid crystal molecules disposed between the upper substrate and the lower substrate can be driven by the fringe field. As a result, the aperture ratio and the front luminescence can be improved.
For the fringe field type liquid crystal display, the common electrode and the pixel electrode are disposed closely to each other or in an overlapped manner. A storage is formed between the common electrode and the pixel electrode. Therefore, the fringe field type liquid crystal display has an advantage in that there is no extra space required for forming the storage in the pixel region. However, when a large area display is formed with a fringe field type, the pixel region becomes larger and the storage becomes larger as well. In that case, the thin film transistor should have also a larger size for driving/charging the enlarged storage for a short time period.
To solve this problem, a thin film transistor having a metal oxide semiconductor material is used because it has high current control characteristics without enlarging the size of the thin film transistor. FIG. 1 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display according to the related art. FIG. 2 is a cross-sectional view illustrating a structure of the thin film transistor substrate of FIG. 1 along line I-I′ according to the related art.
The thin film transistor substrate having a metal oxide semiconductor layer shown in FIGS. 1 and 2 comprises a gate line GL and a data line DL crossing each other with a gate insulating layer GI therebetween on a lower substrate SUB, and a thin film transistor T formed at each crossing portion. By the crossing structure of the gate line GL and the data line DL, a pixel region is defined.
The thin film transistor T comprises a gate electrode G branched (or ‘extruded’) from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D facing the source electrode S and connecting to the pixel electrode PXL, and a semiconductor layer A overlapping the gate electrode G on the gate insulating layer GI for forming a channel between the source electrode S and the drain electrode D.
The semiconductor layer A formed of an oxide semiconductor material has an advantage for a large area thin film transistor substrate having a large charging capacitance due to a high electron mobility of the oxide semiconductor layer. However, the thin film transistor having the oxide semiconductor material may need an etch stopper ES for protecting the upper surface of the semiconductor layer from the etching material for ensuring a stability and characteristics of the thin film transistor. More specifically, an etch stopper ES is needed to protect the semiconductor layer A from an etchant when the source electrode S and the drain electrode D are formed therebetween.
At one end of the gate line GL, a gate pad GP is formed for receiving a gate signal. The gate pad GP is connected to a gate pad terminal GPT through the gate pad contact hole GPH penetrating through the first passivation layer PA1 and the second passivation layer PA2. Further, at one end of the data line DL, a data pad DP is formed for receiving a pixel signal. The data pad DP is connected to a data pad terminal DPT through the data pad contact hole DPH penetrating through the first passivation layer PA1 and the second passivation layer PA2.
In the pixel region, a pixel electrode PXL and a common electrode COM are formed with the second passivation layer PA2 therebetween, to generate a fringe electric field. The common electrode COM is connected to the common line CL disposed in parallel with the gate line GL. The common electrode COM is supplied with a reference voltage (or “common voltage”) via the common line CL.
The common electrode COM and the pixel electrode PXL can have various shapes and positions depending on the design purpose and environment. While the common electrode COM is supplied with a reference voltage having a constant value, the pixel electrode PXL is supplied with a data voltage varying timely according to the video data. Therefore, between the data line DL and the pixel electrode PXL, a parasitic capacitance may be formed. Due to the parasitic capacitance, a video quality of the display may be degraded. Therefore, the common electrode COM is formed first and then the pixel electrode PXL is formed on the topmost layer.
In other words, on the first passivation layer PA1 covering the data line DL and the thin film transistor T, a planarization layer PAC is formed by depositing a thick organic material having a low permittivity. Then, the common electrode COM is formed. And then, after depositing the second passivation layer PA2 to cover the common electrode COM, the pixel electrode PXL overlapping the common electrode is formed on the second passivation layer PA2. In this structure, the pixel electrode PXL is located with distances from the data line DL by the first passivation layer PA1, the planarization layer PAC and the second passivation layer PA2, so that the parasitic capacitance between the data line DL and the pixel electrode PXL can be reduced.
The common electrode COM is formed to be a rectangular shape corresponding to the pixel region. The pixel electrode PXL is formed to have a plurality of segments. Especially, the pixel electrode PXL vertically overlaps the common electrode COM with the second passivation layer PA2 therebetween. Between the pixel electrode PXL and the common electrode COM, the fringe electric field is formed. By this fringe electric field, the liquid crystal molecules arrayed in plane direction between the thin film transistor substrate and the color filter substrate may be rotated according to the dielectric anisotropy of the liquid crystal molecules. According to the rotation degree of the liquid crystal molecules, the light transmittance ratio of the pixel region may be changed so as to represent a desired gray scale.
The pads GP and DP are exposed by patterning insulating layers covering them. The exposed pads GP and DP are covered by the pad terminals GPT and DPT formed by the transparent conductive material used for the pixel electrode PXL. Further, the pad for the common electrode COM is also exposed by patterning the second passivation layer PA2.
At the pad area, for receiving signals from the outside controller, the insulating layers are patterned for exposing the pads. However, as described above, the number and kinds of the insulation layers covering the pad are different. Thus, the exposed pads may have damage. Hereinafter, referring to FIGS. 3 and 4, the damage which occurred at the pads is explained as follows. FIG. 3 is a cross sectional view illustrating a process for forming a contact hole exposing pads of the fringe field switching type liquid crystal display according to the related art. FIG. 4 is a cross sectional view illustrating damages occurred at the pads after etching the insulating layers used by the method shown in FIG. 3.
Referring to FIG. 3, at the pad area of the fringe field switching type liquid crystal display, a gate pad GP, a data pad DP and a common pad CP are disposed. The gate pad GP is one end portion of the gate line GL. The data pad DP is one end portion of the data line DL. The common pad CP is one end of the common line CL.
On the gate pad GP, a gate insulating layer GI, a first passivation layer PA1 and a second passivation layer PA2 are sequentially formed. On the data pad DP, the first passivation layer PA1 and the second passivation layer PA2 are stacked. On the contrary, on the common pad CP, only the second passivation layer PA2 is disposed. In order to expose portions of the gate pad GP, the data pad DP and the common pad CP at the same time using one mask process, the gate insulating layer GI, the first passivation layer PA1 and the second passivation layer PA2 needs to be patterned in one etching step.
At the gate pad GP, to form a gate contact hole GPH, three insulating layers need to be etched with the sequence of {circle around (1)}→{circle around (2)}→{circle around (3)}. Consequently, at the data pad DP, to form a data contact hole DPH, two insulating layers need to be etched with the sequence of {circle around (1)}→{circle around (2)}. Simultaneously, at the common pad CP, to form a common contact hole CPH, one insulating layer {circle around (1)} needs to be etched.
When portions of the gate pad GP, the common pad CP and the data pad DP are etched, these pads are constantly exposed to the etchant. As the data pad DP includes a metal material such as copper, it may not be damaged by the etchant for patterning the insulating layers even though it is affected by the etchant during the gate pad GP is exposed. On the other hand, the common pad CP is formed of a transparent conductive material such as indium-tin oxide and indium-zinc oxide. Therefore, these transparent conductive materials can be easily damaged by the etchant when the gate pad GP is exposed.
By being exposed to the etchant, the transparent conductive material can be partially crystallized so that grains can be formed. As boundaries of the grains are easily damaged by the etchant used in the dry etching process for patterning the insulating layers. Then, the second passivation layer PA2 disposed under the damaged transparent conductive material can be etched away. For example, trench shaped patterns can be formed at the second passivation layer PA2 as shown in FIG. 4. Such patterns can not properly protect the conductive layer thereunder. When electrical signals are supplied through such defective patterns, an electrical insulation property cannot be ensured by these defective patterns so that the signals cannot be properly applied to the pixel electrode. Consequently, video images of the LCD display can be defective.